Displays and light-projectors using arrays of MEMS devices such as the micromirrors of Digital Micromirror Devices™ (DMD's) have been developed for a number of applications. (“Digital Micromirror Device™” is a trademark of Texas Instruments.) For some applications, DMD's include a static random-access memory (SRAM) for storing image data and addressing the array of micromirrors. Thus, the DMD SRAM's have used memory cells having a single static memory cell per pixel. Typically, each mirror in an array of mirrors is suspended above an individual SRAM cell in a corresponding array of memory cells. Address electrodes are connected to the SRAM nodes at which “1” or “0” voltages are set.
Electrostatic forces applied between the address electrodes and the mirrors rotate the mirrors about an axis. The rotation is stopped at predetermined angles, limited by touching of an edge of the mirror at the substrate. Gray scale in images is accomplished by using pulse width modulation of the binary ON (1) and OFF (0) times of each mirror. Such digital operation of DMD's and other MEMS-based display arrays imposes bandwidth requirements on the display's circuitry for filling the array with data for each frame to be displayed.
Some DMD displays take advantage of mechanical latching of the mirrors and some DMD displays utilize architectures having SRAM's smaller than the micromirror array, in the sense of having a number of SRAM cells that is a fraction of the number of micromirrors in the micromirror array. In such architectures, the peak data rate can be made comparable to the average data rate. As faster and larger arrays of MEMS devices are developed for displays and other applications, further reduction of bandwidth is a very desirable goal, especially if it can be achieved in a way that does not depend on particular physical characteristics of the MEMS devices in the array.